// SPDX-License-Identifier: GPL-2.0+
/*
 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
 *
 * Copyright (C) 2010 Extreme Engineering Solutions.
 */

#include <stdio.h>
#include <stdlib.h>
#include <sys/io.h>
#include <stdint.h>
#define GPIOBASE 0x1c00
void set_gpio(int gpio, int high)
{
uint16_t addr = GPIOBASE + 0x100 + gpio * 8;
uint32_t val = inl(addr);
if (high)
    val |= 0x80000000;
else
    val &= ~0x80000000;
outl(val, addr);
printf("GPIO%d = %s (0x%08x)\n",
       gpio,
       high ? "HIGH" : "LOW",
       val);
}
int main(int argc, char* argv[])
{
    if (ioperm(GPIOBASE, 0x400, 1)) {
        perror("ioperm");
        return 1;
    }
    set_gpio(atoi(argv[1]), atoi(argv[2]));
    return 0;
}

// SPDX-License-Identifier: GPL-2.0
/*
 * Simple GPIO driver for Intel Lynxpoint PCH (IO port based)
 * GPIOBASE = 0x1c00, 95 pins
 * Each pin has two 32-bit config registers at: 0x100 + pin*8  (CONFIG1)
 * and 0x104 + pin*8 (CONFIG2).
 *
 * CONFIG1 bits:
 *  31: OUT_LVL
 *  30: IN_LVL
 *  2:  DIR (0=output, 1=input)
 *  1-0: USE_SEL (must be 01 for GPIO mode)
 *
 * CONFIG2 bits:
 *  2: GPINDIS (input disable, we keep 0)
 *  1-0: pull up/down (not used here)
 */

#include <linux/module.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>

#define DRIVER_NAME "simple_lp_gpio"
#define GPIO_BASE 0x1c00
#define GPIO_NUM  95

#define CONFIG1_OFFSET(n) (0x100 + (n) * 8)
#define CONFIG2_OFFSET(n) (0x104 + (n) * 8)

#define OUT_LVL_BIT   BIT(31)
#define IN_LVL_BIT    BIT(30)
#define DIR_BIT       BIT(2)
#define USE_SEL_MASK  GENMASK(1, 0)
#define USE_SEL_GPIO  1

static void __iomem *gpio_base;   /* ioport mapped virtual address */

static int simple_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
    u32 val = ioread32(gpio_base + CONFIG1_OFFSET(offset));
    return !!(val & IN_LVL_BIT);
}

static int simple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
    void __iomem *reg = gpio_base + CONFIG1_OFFSET(offset);
    u32 val = ioread32(reg);

    if (value)
        val |= OUT_LVL_BIT;
    else
        val &= ~OUT_LVL_BIT;

    iowrite32(val, reg);
    return 0;
}

static int simple_gpio_dir_input(struct gpio_chip *chip, unsigned int offset)
{
    void __iomem *reg = gpio_base + CONFIG1_OFFSET(offset);
    u32 val = ioread32(reg);

    /* set direction to input (DIR_BIT = 1) */
    val |= DIR_BIT;
    /* ensure GPIO mode */
    val = (val & ~USE_SEL_MASK) | USE_SEL_GPIO;

    iowrite32(val, reg);
    return 0;
}

static int simple_gpio_dir_output(struct gpio_chip *chip, unsigned int offset, int value)
{
    void __iomem *reg = gpio_base + CONFIG1_OFFSET(offset);
    u32 val = ioread32(reg);

    /* first set output level */
    if (value)
        val |= OUT_LVL_BIT;
    else
        val &= ~OUT_LVL_BIT;

    /* then set direction to output (DIR_BIT = 0) */
    val &= ~DIR_BIT;
    /* ensure GPIO mode */
    val = (val & ~USE_SEL_MASK) | USE_SEL_GPIO;

    iowrite32(val, reg);
    return 0;
}

static int simple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
    u32 val = ioread32(gpio_base + CONFIG1_OFFSET(offset));
    if (val & DIR_BIT)
        return GPIO_LINE_DIRECTION_IN;
    else
        return GPIO_LINE_DIRECTION_OUT;
}

static struct gpio_chip simple_gpio_chip = {
    .label = DRIVER_NAME,
    .owner = THIS_MODULE,
    .get = simple_gpio_get,
    .set = simple_gpio_set,
    .direction_input = simple_gpio_dir_input,
    .direction_output = simple_gpio_dir_output,
    .get_direction = simple_gpio_get_direction,
    .base = -1,                  /* dynamic base */
    .ngpio = GPIO_NUM,
    .can_sleep = false,
};

static int simple_gpio_probe(struct platform_device *pdev)
{
    struct resource *res;
    int ret;

    res = platform_get_resource(pdev, IORESOURCE_IO, 0);
    if (!res) {
        dev_err(&pdev->dev, "No IO resource found\n");
        return -ENODEV;
    }

    /* request the IO port region */
    if (!request_region(res->start, resource_size(res), DRIVER_NAME)) {
        dev_err(&pdev->dev, "IO region 0x%lx busy\n", (unsigned long)res->start);
        return -EBUSY;
    }

    /* ioport_map gives us a virtual address to use with ioread32/iowrite32 */
    gpio_base = ioport_map(res->start, resource_size(res));
    if (!gpio_base) {
        dev_err(&pdev->dev, "ioport_map failed\n");
        release_region(res->start, resource_size(res));
        return -ENOMEM;
    }

    ret = gpiochip_add_data(&simple_gpio_chip, NULL);
    if (ret) {
        dev_err(&pdev->dev, "Failed to register gpio chip: %d\n", ret);
        ioport_unmap(gpio_base);
        release_region(res->start, resource_size(res));
        return ret;
    }

    platform_set_drvdata(pdev, &simple_gpio_chip);
    dev_info(&pdev->dev, "Registered %d GPIOs at IO 0x%lx\n", GPIO_NUM, (unsigned long)res->start);
    return 0;
}

static void simple_gpio_remove(struct platform_device *pdev)
{
    struct gpio_chip *chip = platform_get_drvdata(pdev);
    struct resource *res = platform_get_resource(pdev, IORESOURCE_IO, 0);

    gpiochip_remove(chip);
    if (res) {
        ioport_unmap(gpio_base);
        release_region(res->start, resource_size(res));
    }
}

static struct platform_driver simple_gpio_driver = {
    .probe = simple_gpio_probe,
    .remove = simple_gpio_remove,
    .driver = {
        .name = DRIVER_NAME,
    },
};

static struct platform_device *simple_gpio_device;

static int __init simple_gpio_init(void)
{
    int ret;

    /* register platform driver */
    ret = platform_driver_register(&simple_gpio_driver);
    if (ret)
        return ret;

    /* create platform device with IO resource */
    simple_gpio_device = platform_device_alloc(DRIVER_NAME, -1);
    if (!simple_gpio_device) {
        platform_driver_unregister(&simple_gpio_driver);
        return -ENOMEM;
    }

    struct resource res = {
        .start = GPIO_BASE,
        .end   = GPIO_BASE + 0x3ff,   /* cover 0x1c00 - 0x1fff */
        .flags = IORESOURCE_IO,
    };
    ret = platform_device_add_resources(simple_gpio_device, &res, 1);
    if (ret)
        goto err;

    ret = platform_device_add(simple_gpio_device);
    if (ret)
        goto err;

    return 0;

err:
    platform_device_put(simple_gpio_device);
    platform_driver_unregister(&simple_gpio_driver);
    return ret;
}

static void __exit simple_gpio_exit(void)
{
    platform_device_unregister(simple_gpio_device);
    platform_driver_unregister(&simple_gpio_driver);
}

module_init(simple_gpio_init);
module_exit(simple_gpio_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Your Name");
MODULE_DESCRIPTION("Simple GPIO driver for Intel Lynxpoint PCH (IO port based)");

static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
	{ "INT33C7", (kernel_ulong_t)&lptlp_soc_data },
	{ "INT3437", (kernel_ulong_t)&lptlp_soc_data },
	{ }
};
MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);

static struct platform_driver lp_gpio_driver = {
	.probe          = lp_gpio_probe,
	.driver         = {
		.name   = "lp_gpio",
		.pm	= pm_sleep_ptr(&lp_gpio_pm_ops),
		.acpi_match_table = lynxpoint_gpio_acpi_match,
	},
};

DefinitionBlock ("", "SSDT", 2, "INTEL", "GPIOLP", 0x00000000)
{
    External (\_SB_.PCI0.LPCB, DeviceObj)
    Scope (\_SB_.PCI0.LPCB)
    {
        Device (GPO0)
        {
            Name (_HID, "INT33C7")
            Name (_UID, Zero)
            Name (_DDN, "Intel GPIO Controller")
            Name (_CRS, ResourceTemplate ()
            {
                // 覆盖 0x1C00 ~ 0x1CFF
                IO (Decode16, 0x1C00, 0x1C00, 0x01, 0xFF)
                // 覆盖 0x1D00 ~ 0x1DFF
                IO (Decode16, 0x1D00, 0x1D00, 0x01, 0xFF)
                // 覆盖 0x1E00 ~ 0x1EFF
                IO (Decode16, 0x1E00, 0x1E00, 0x01, 0xFF)
                // 覆盖 0x1F00 ~ 0x1FFF
                IO (Decode16, 0x1F00, 0x1F00, 0x01, 0xFF)
            })
            Method (_STA, 0, NotSerialized)
            {
                Return (0x0F)
            }
        }
    }
}